Semiconductor integrated circuits comprise a multiplicity of transistor devices integrated at a major surface of a semiconductor medium, typically a monocrystalline silicon or gallium arsenide semiconductor chip. Silicon dioxide layers are useful in these integrated circuits for serving such purposes as gate oxide dielectric layers of MOS (metal oxide semiconductor) transistors and as passivation oxide dielectric layers located on the major surface of the semiconductor between transistors (whether MOS or not) for mutually electrically isolating the transistors.
In the art of MOS transistors in VLSI (very large scale integrated) circuits, the lateral size of each transistor is made as small as possible in order to fit as many transistors as possible on the major surface of a single semiconductor chip and to enhance the speed of circuit operation. As the lateral size of the transistor is thus made smaller, the thickness of the silicon dioxide gate dielectric ("gate oxide") layer separating the gate electrode of an MOS transistor from the underlying major surface of the semiconductor body ideally should be made correspondingly (but not necessarily linearly) smaller. More specifically, as the length of the gate channel (source-to-drain) in an MOS transistor is reduced to lengths below one micron, the thickness of the gate oxide is thus made smaller than about 200 Angstroms; however, impurities from the overlying gate electrode can then undesirably penetrate through the gate oxide to the interface of the oxide with the underlying semiconductor and thereby cause undesirable transistor threshold voltage shifts.
It is known in the art that the use of a silicon nitroxide (oxynitride) layer overlying a silicon dioxide layer as a gate oxide of an MOS transistor can act as an effective barrier (or seal) against the undesirable penetration through the gate oxide by many impurities--such as boron, oxygen, nitrogen, sodium, arsenic, and phosphorus (but not water). It is also known in the art that silicon nitroxide layers that contain nitrogen in an amount corresponding to a nitrogen atomic concentration fraction [N/(N+0)] (simply called "nitrogen fraction" W" hereafter) in the approximate range of 0.10 to 0.20, especially approximately 0.12 to 0.14, are extremely effective barriers against both oxygen and silicon diffusion.
It is further known in the art that the surface of a silicon nitride layer decomposes rapidly at high temperatures in an oxygen ambient. The product of this decomposition is a silicon nitroxide layer whose composition ranges from almost pure oxide to almost pure nitride; therefore, in particular, a region of this layer has a nitrogen atomic fraction of about 0.12 to 0.14, and it is this region that is believed to be responsible for the effective barrier posed by the "silicon nitride" layer (compound layer of silicon nitroxide on silicon nitride) against the diffusion of oxygen.
Thus, workers in the art have proposed using a silicon nitroxide layer as a barrier layer for such purposes as sealing the gate oxide of an MOS transistor against undesirable diffusants. Such sealing in the case of an n-channel MOS transistor is needed in particular for protecting the oxide-semiconductor interface against the diffusion of arsenic or phosphorus (which is ordinarily used to dope the polysilicon gate electrode) from the gate electrode through the gate oxide; in the case of a p-channel transistor, against the diffusion of boron. Since boron (as well as some of its compounds) diffuses through the oxide more easily than arsenic or phosphorus, the problem of diffusion of impurities through the gate oxide can impose a more severe lower limit upon the gate oxide thickness in the case of p-channel MOS transistors (about 400 Angstroms) than in the case of n-channel transistors (about 100 to 200 Angstroms). Prior art techniques for thus sealing a thin gate oxide layer include forming such a silicon nitroxide layer at the top of the oxide layer, as by nitriding a silicon dioxide layer by heating it in ammonia gas. However, these techniques have resulted not only in the formation of the desired silicon nitroxide at the top of the gate oxide but also in an undesirable diffusion of significant amounts of nitrogen through the gate oxide to regions near the underlying silicon semiconductor to form nitrogen fractions higher than 0.13 whereby undesirable large numbers of trapping centers are formed that are deleterious to MOS transistor operation. Moreover, the formation of a silicon nitroxide barrier layer at the top of the gate oxide layer entails the presence of trapping centers in the nitroxide. During operation of the transistor, these trapping centers can become electrically charged by reason of, for instance, energetic ("hot") electrons from the semiconductor drifting into and occupying these centers, which can further adversely affect transistor operation by uncontrollably changing the transistor threshold voltage. Furthermore, during the prolonged high temperature treatments used in prior art to form the nitroxide layer, whether on a gate oxide of a single MOS transistor or on an isolation oxide between transistors (whether MOS or not), there can occur in the semiconductor itself an undesirable diffusion of impurities previously introduced into the semiconductor, whereby the impurity regions in the semiconductor (p-tubs, n-tubs, channel implants, channel stops) are undesirably affected not only by undesirable changes of impurity concentrations therein but also by undesirable movements of the junction profiles that define the boundaries between contiguous regions of opposite (p and n) conductivity types or of the same types but differing conductivity magnitudes.
It would therefore be desirable to have an integrated circuit comprising a silicon nitride barrier layer on a silicon dioxide dielectric layer that mitigates the problems in the prior art.